Content addressable memories are well known in the art. These memories provide the function of comparing data applied to the memory with data already stored in the memory and providing an indication as to whether or not the applied data is the same as the stored data. Such functions find application in large memory systems to identify the locations of blocks of data or programs. As is often the case with design efforts in large scale integrated circuits (LSI) and very large scale integrated circuits (VLSI) there is an ongoing effort to reduce the number of components, and thus the physical area required to implement a particular function. It is also another goal in such design to increase the speed with which the circuitry responds. Thus, there is a continuing effort to provide the subject functions in a smaller area and with faster response than that which is present in the prior art. Among the problems associated with driving the data input lines of a content addressable memory, and in fact in connection with the driving of any input lines which are associated with precharged lines, is that glitches or small disturbances are sometimes present on the output line during the transition of the driver from its quiescence state to its asserted state. These glitches or other disturbances do not accurately reflect the steady state logic state of the driver circuit. This can frustrate any attempts to precharge circuits which are being driven by the self-blocking driver in that the glitches or disturbances may cause the premature discharging of the precharged lines.